Silicon Labs /Series1 /EFM32GG11B /EFM32GG11B320F2048GQ100 /LESENSE /ROUTEPEN

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as ROUTEPEN

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CH0PEN)CH0PEN 0 (CH1PEN)CH1PEN 0 (CH2PEN)CH2PEN 0 (CH3PEN)CH3PEN 0 (CH4PEN)CH4PEN 0 (CH5PEN)CH5PEN 0 (CH6PEN)CH6PEN 0 (CH7PEN)CH7PEN 0 (CH8PEN)CH8PEN 0 (CH9PEN)CH9PEN 0 (CH10PEN)CH10PEN 0 (CH11PEN)CH11PEN 0 (CH12PEN)CH12PEN 0 (CH13PEN)CH13PEN 0 (CH14PEN)CH14PEN 0 (CH15PEN)CH15PEN 0 (ALTEX0PEN)ALTEX0PEN 0 (ALTEX1PEN)ALTEX1PEN 0 (ALTEX2PEN)ALTEX2PEN 0 (ALTEX3PEN)ALTEX3PEN 0 (ALTEX4PEN)ALTEX4PEN 0 (ALTEX5PEN)ALTEX5PEN 0 (ALTEX6PEN)ALTEX6PEN 0 (ALTEX7PEN)ALTEX7PEN

Description

I/O Routing Register

Fields

CH0PEN

CH0 Pin Enable

CH1PEN

CH1 Pin Enable

CH2PEN

CH2 Pin Enable

CH3PEN

CH3 Pin Enable

CH4PEN

CH4 Pin Enable

CH5PEN

CH5 Pin Enable

CH6PEN

CH6 Pin Enable

CH7PEN

CH7 Pin Enable

CH8PEN

CH8 Pin Enable

CH9PEN

CH9 Pin Enable

CH10PEN

CH10 Pin Enable

CH11PEN

CH11 Pin Enable

CH12PEN

CH12 Pin Enable

CH13PEN

CH13 Pin Enable

CH14PEN

CH14 Pin Enable

CH15PEN

CH15 Pin Enable

ALTEX0PEN

ALTEX0 Pin Enable

ALTEX1PEN

ALTEX1 Pin Enable

ALTEX2PEN

ALTEX2 Pin Enable

ALTEX3PEN

ALTEX3 Pin Enable

ALTEX4PEN

ALTEX4 Pin Enable

ALTEX5PEN

ALTEX5 Pin Enable

ALTEX6PEN

ALTEX6 Pin Enable

ALTEX7PEN

ALTEX7 Pin Enable

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